1. Field of the Invention
The present invention relates to modules having semiconductor devices mounted on a wiring or circuit board, and more particularly to a technique directed to making an arrangement in which data can be output from the semiconductor devices at the same timing as an external clock.
2. Description of the Related Art
Conventionally, a module is formed by mounting a plurality of semiconductor devices on a circuit device. For example, a memory module is formed by mounting a plurality of semiconductor memory devices on a wiring board (which may be referred to as a circuit board).
FIG. 1 is a block diagram of a conventional memory module (first conventional example). A memory module 10 shown in FIG. 1 includes a wiring board 150, in which provided are semiconductor memory devices 100 through 107, a PLL (Phase-Locked Loop) circuit 11, and a plurality of data input/output terminals DA and a clock input terminal respectively provided for the memory devices 100 through 107. The memory module 10 inputs and outputs parallel data consisting of a plurality of bits via the data input/output terminals DQ, and receives an external clock via the clock input terminal CLK.
The memory devices 100 through 107 input and output data signals DQ via data input/output terminals DQ* connected to the data input/output terminals DQ.
The clock supplied from the outside of the memory module 10 is applied to the PLL circuit 11 via the clock input terminal CLK. A clock output by the PLL circuit 11 is supplied to clock input terminals CLK* of the memory devices 100 through 107. The PLL circuit 11 is used to operate the memory module 10 in synchronism with a high-speed clock. If the external clock is supplied directly to the memory devices 100 through 107, the clock waveform will be rounded due to the parasitic capacitance coupled to clock supply lines extending from the clock input terminal CLK to the memory devices 100 through 107. The rounded clock waveform would prevent the memory devices 100 through 107 from operating at high speed. As an increased number of memory devices 100 through 107 is used, the clock waveform will be rounded more greatly. The PLL circuit 11 acts to reduce the parasitic capacitance of the clock supply lines and enhance the driving ability of the clock, so that the highly precise clock can be supplied to the memory devices 100 through 107. If the clock supply lines that extend from the PLL circuit 11 to the memory devices 100 through 107 are arranged so as to have an identical length, the input timings of the clocks obtained at clock input terminals CLK* of the memory devices 100-107 will coincide with one another.
FIG. 2 is a block diagram of the periphery of the PLL circuit 11 mounted on the wiring board 150 of the memory module 10, and the internal structure of the memory device 100 also mounted thereon. FIG. 3 is a timing chart of an operation of the memory module 10. Although only the memory device 100 is illustrated in FIGS. 2 and 3, the other memory devices 101 through 107 are configured as the memory device 100, and operate in the same manner as the same.
The memory module 10 is configured so that the timing relationship of the signals applied to its data input/output terminals DQ and clock input terminal CLK can be maintained at the data input/output terminals DQ* and clock input terminals CLK* of the memory devices 100 through 107. The external clock is supplied to the PLL circuit 11 as clock CLK1 via the clock input terminal CLK and a delay circuit 21. A clock CLK2, that is output by the PLL circuit 11, is supplied, as clock CLK3, to the clock input terminal CLK* of the memory device 100 via a clock supply line 23 having a tree-like structure, and is fed back, as a clock CLK4, to the input side of the PLL circuit 11 via a delay line 22. The PLL circuit 11 controls the phase (output timing) of the clock CLK2 so that the clocks CLK1 and CLK4 are in phase.
The delay circuit 21 has a meander wiring pattern, which has a delay time (delay amount) D1′ that is substantially equal to a delay time (delay amount) D1 of a data line (data bus) 24 for connecting the data input/output terminal DQ of the memory module 150 and the data input/output terminal DQ* of the memory device 100. The delay circuit 22 has a meander wiring pattern, which has a delay time (delay amount) D2′ that is substantially equal to a delay time (delay amount) D2 of a clock supply line 23. The PLL circuit 11 adjusts the phase of the clock CLK2 so that the clocks CLK1 and CLK4 are in phase with each other. As a result of the above phase control, the timing relationship of the signals applied to the data input/output terminal DQ and the clock input terminal CLK is also maintained at the data input/output terminal DQ* and clock input terminal CLK* of the memory device 100.
The memory device 100 includes a data output buffer 110, a data input buffer 111, a clock input buffer 112, and a DLL (Delay-Locked Loop) circuit 113 for outputting a clock. The DLL circuit 113 may be replaced by a PLL circuit. The clock CLK3 applied to the clock input terminal CLK* is supplied to the data input buffer 111 and the DLL circuit 113 via the input buffer 112. The data input buffer 111 fetches input data applied to the data input/output terminal DQ* in synchronism with the clock CLK3 available via the input buffer 112. The DLL circuit 113 supplies the data output buffer 110 with a clock CLK10 for data outputting. The clock CLK10 can be obtained by delaying the clock CLK3. By setting the delay time between the clock CLK3 and the clock CLK10 appropriately, the memory device 100 can output data to the data input/output terminal DQ* at the same timing as the clock CLK3. That is, the clock CLK10 leads to the clock CLK3 applied to the clock input terminal CLK* by a delay D4 of the data output buffer 110.
In the memory module thus configured, as shown in FIG. 3, data output to the data input/output terminal lags behind the clock CLK applied to the clock input terminal CLK by D1×2.
FIG. 4 is a block diagram of another conventional memory module (second conventional module) that has a different configuration from the first conventional memory module. A memory module 12 shown in FIG. 4 has a unique arrangement that makes it possible to operate at a higher speed than that in the memory module 10. More particularly, the data input/output terminals DQ of the memory module 12 and the data input/output terminals DQ* are arranged as close as possible. The PLL circuit 11 is arranged so as to split memory devices 100A through 107A into two groups. The clock supply line 23 from the PLL circuit 11 is arranged in a tree fashion on the side of the wiring board 150 opposite to that on which the data input/output terminals DQ are provided. The data input/output terminals DQ* and clock input terminals CLK* of the memory modules 100A through 107A are arranged on the opposite sides of the chips. This terminal arrangement is different from that of the memory modules 100 through 107.
FIG. 5 is a block diagram of the periphery of the PLL circuit 11 mounted on the wiring board 150 of the memory module 12, and the internal structure of the memory device 101A also mounted thereon. For the sake of convenience, the data input/output terminal DQ* and the clock input terminal CLK* are arranged on the same side of the memory device 100A. FIG. 6 is a timing chart of an operation of the memory module 12 shown in FIG. 5. Although only the memory device 100A is illustrated in FIGS. 5 and 6, the other memory devices 101A through 107A are configured as the memory device 100A, and operate in the same manner as the same.
In FIG. 5, the data lines 24 are too short to cause a substantial delay. Hence, the clock input terminal CLK and the PLL circuit 11 are connected directly. In the data outputting operation, the output data DQ at the data input/output terminal DQ is in phase with the external clock at the clock input terminal CLK. In contrast, in the memory module 10, the output data DQ is delayed so as to lag behind the clock at the clock input terminal CLK by the delay D1×2, as has been described previously.
The data are output from the memory devices 100 through 107 mounted on the memory module 10 at the timings adjusted by the DLL (or PLL) circuit 113 also mounted thereon. The DLL 113 needs a stable power source in order to perform highly precise timing adjustment. However, the DLL circuit 113 is provided in each of the memory devices 100 through 107, and is therefore affected by noise superimposed on a power supply thereto. This will cause an error in timing adjustment and a jitter between the phase of the clock and that of the output data.
The above drawbacks occur in the memory module 12 as well.